sn54hc125, SN74HC125 quadruple bus buffer gates with 3-state outputs scls104b march 1984 revised may 1997 1 post office box 655303 ? dallas, texas 75265 high-current 3-state outputs interface directly with system bus or can drive up to 15 lsttl loads package options include plastic small-outline (d), shrink small-outline (db), and ceramic flat (w) packages, ceramic chip carriers (fk), and standard plastic (n) and ceramic (j) 300-mil dips description these quadruple bus buffer gates feature independent line drivers with 3-state outputs. each output is disabled when the associated output-enable (oe ) input is high. the sn54hc125 is characterized for operation over the full military temperature range of 55 c to 125 c. the SN74HC125 is characterized for operation from 40 c to 85 c. function table (each buffer) inputs output oe a y l h h l ll h x z logic symbol 2 en 1 2 1a 1y 3 4 5 2a 2y 6 10 9 3a 3y 8 13 12 4a 4y 11 1oe 2oe 3oe 4oe 2 this symbol is in accordance with ansi/ieee std 91-1984 and iec publication 617-12. pin numbers shown are for the d, db, j, n, and w packages. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 1 2 3 4 5 6 7 14 13 12 11 10 9 8 1oe 1a 1y 2oe 2a 2y gnd v cc 4oe 4a 4y 3oe 3a 3y sn54hc125 ...j or w p ackage SN74HC125 . . . d, db, or n package (top view) 3212019 910111213 4 5 6 7 8 18 17 16 15 14 4a nc 4y nc 3oe 1y nc 2oe nc 2a 1a 1oe nc 3y 3a v 4oe 2y gnd nc sn54hc125 . . . fk package (top view) cc nc no internal connection copyright ? 1997, texas instruments incorporated production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
sn54hc125, SN74HC125 quadruple bus buffer gates with 3-state outputs scls104b march 1984 revised may 1997 2 post office box 655303 ? dallas, texas 75265 logic diagram (positive logic) 1 1oe 2 1a 1y 3 4 2oe 5 2a 2y 6 10 3oe 9 3a 3y 8 13 4oe 12 4a 4y 11 pin numbers shown are for the d, db, j, n, and w packages. absolute maximum ratings over operating free-air temperature range 2 supply voltage range, v cc 0.5 v to 7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input clamp current, i ik (v i < 0 or v i > v cc ) (see note 1) 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output clamp current, i ok (v o < 0 or v o > v cc ) (see note 1) 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous output current, i o (v o = 0 to v cc ) 35 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous current through v cc or gnd 70 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . package thermal impedance, q ja (see note 2): d package 127 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . db package 158 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . n package 78 c/w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditi onso is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. notes: 1. the input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. the package thermal impedance is calculated in accordance with jesd 51, except for through-hole packages, which use a trace length of zero. recommended operating conditions sn54hc125 SN74HC125 unit min nom max min nom max unit v cc supply voltage 2 5 6 2 5 6 v v cc = 2 v 1.5 1.5 v ih high-level input voltage v cc = 4.5 v 3.15 3.15 v v cc = 6 v 4.2 4.2 v cc = 2 v 0 0.5 0 0.5 v il low-level input voltage v cc = 4.5 v 0 1.35 0 1.35 v v cc = 6 v 0 1.8 0 1.8 v i input voltage 0 v cc 0 v cc v v o output voltage 0 v cc 0 v cc v v cc = 2 v 0 1000 0 1000 t t input transition (rise and fall) time v cc = 4.5 v 0 500 0 500 ns v cc = 6 v 0 400 0 400 t a operating free-air temperature 55 125 40 85 c
sn54hc125, SN74HC125 quadruple bus buffer gates with 3-state outputs scls104b march 1984 revised may 1997 3 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions v cc t a = 25 c sn54hc125 SN74HC125 unit parameter test conditions v cc min typ max min max min max unit 2 v 1.9 1.998 1.9 1.9 i oh = 20 m a 4.5 v 4.4 4.499 4.4 4.4 v oh v i = v ih or v il 6 v 5.9 5.999 5.9 5.9 v i oh = 6 ma 4.5 v 3.98 4.3 3.7 3.84 i oh = 7.8 ma 6 v 5.48 5.8 5.2 5.34 2 v 0.002 0.1 0.1 0.1 i ol = 20 m a 4.5 v 0.001 0.1 0.1 0.1 v ol v i = v ih or v il 6 v 0.001 0.1 0.1 0.1 v i ol = 6 ma 4.5 v 0.17 0.26 0.4 0.33 i ol = 7.8 ma 6 v 0.15 0.26 0.4 0.33 i i v i = v cc or 0 6 v 0.1 100 1000 1000 na i oz v o = v cc or 0 6 v 0.01 0.5 10 5 m a i cc v i = v cc or 0, i o = 0 6 v 8 160 80 m a c i 2 v to 6 v 3 10 10 10 pf switching characteristics over recommended operating free-air temperature range, c l = 50 pf (unless otherwise noted) (see figure 1) parameter from to v cc t a = 25 c sn54hc125 SN74HC125 unit parameter (input) (output) v cc min typ max min max min max unit 2 v 48 120 150 150 t pd a y 4.5 v 14 24 36 30 ns 6 v 11 20 25 26 2 v 53 120 180 150 t en oe y 4.5 v 14 24 36 30 ns 6 v 11 20 31 26 2 v 30 120 180 150 t dis oe y 4.5 v 15 24 36 30 ns 6 v 14 20 31 26 2 v 28 60 90 75 t t any 4.5 v 8 12 18 15 ns 6 v 6 10 15 13
sn54hc125, SN74HC125 quadruple bus buffer gates with 3-state outputs scls104b march 1984 revised may 1997 4 post office box 655303 ? dallas, texas 75265 switching characteristics over recommended operating free-air temperature range, c l = 150 pf (unless otherwise noted) (see figure 1) parameter from to v cc t a = 25 c sn54hc125 SN74HC125 unit parameter (input) (output) v cc min typ max min max min max unit 2 v 67 150 225 190 t pd a y 4.5 v 19 30 45 38 ns 6 v 15 25 39 32 2 v 100 135 200 170 t en oe y 4.5 v 20 27 40 34 ns 6 v 17 23 34 29 2 v 45 210 315 265 t t any 4.5 v 17 42 63 53 ns 6 v 13 36 53 45 operating characteristics, t a = 25 c parameter test conditions typ unit c pd power dissipation capacitance per gate no load 45 pf
sn54hc125, SN74HC125 quadruple bus buffer gates with 3-state outputs scls104b march 1984 revised may 1997 5 post office box 655303 ? dallas, texas 75265 parameter measurement information voltage waveform input rise and fall times 50% 50% 10% 10% 90% 90% v cc 0 v t r t f input voltage waveforms propagation delay and output transition times 50% 50% 50% 10% 10% 90% 90% v cc v oh v ol 0 v t r t f input in-phase output 50% t plh t phl 50% 50% 10% 10% 90% 90% v oh v ol t r t f t phl t plh out-of-phase output 50% 10% 90% v cc v cc v ol 0 v output control (low-level enabling) output waveform 1 (see note b) 50% t pzl t plz voltage waveforms enable and disable times for 3-state outputs v oh 0 v 50% 50% t pzh t phz output waveform 2 (see note b) v cc test point from output under test c l (see note a) r l v cc s1 s2 load circuit parameter c l t pzh t pd or t t t dis t en t pzl t phz t plz 1 k w 1 k w 50 pf or 150 pf 50 pf open closed r l s1 closed open s2 open closed closed open 50 pf or 150 pf open open notes: a. c l includes probe and test-fixture capacitance. b. waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. c. phase relationships between waveforms were chosen arbitrarily. all input pulses are supplied by generators having the followi ng characteristics: prr 1 mhz, z o = 50 w , t r = 6 ns, t f = 6 ns. d. the outputs are measured one at a time with one input transition per measurement. e. t plz and t phz are the same as t dis . f. t pzl and t pzh are the same as t en . g. t plh and t phl are the same as t pd . figure 1. load circuit and voltage waveforms
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (acritical applicationso). ti semiconductor products are not designed, authorized, or warranted to be suitable for use in life-support devices or systems or other critical applications. inclusion of ti products in such applications is understood to be fully at the customer's risk. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 1998, texas instruments incorporated
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